The Intel486 uses a two level paging scheme to translate the virtual address into physical address. All page frames are of 4K bytes which simplifies allocation and reallocation of memory. The linear address consists of three parts:
Bits 0 - 11 OFFSET used to calculate the offset within the page frame Bits 12 - 21 LD1 used to locate the page frame Bits 22 - 31 LD2 used as an index for the top level page table (page directory)
The page directory is 4K bytes long and allows up to 1024 page directory entries; each entry is a double word. An entry contains
Each page table holds up to 1024 page table entries. Each page table entry contains the starting address of the page frame and statistical information. Address bits 12-21 are used to select the page table entry. The higher order 20 bits are used to find the actual physical address.
The lower order 12 bits of the page directory or table entries contain statistical information about page tables or pages respectively. The P bit set to 0 indicates that the entry can not be used for address translation; whereas P = 1 indicates that the address can be used for translation. Bit 5 is set by the microprocessor for both types of entries before a read/write access occurs to an address covered by the entry. The "dirty bit" (Bit 6) is set to 1 before the contents corresponding to the page table are modified. The bits 9, 10 and 11 are reserved for operating system to keep track of the "age" of the page in memory or when it was last referenced which is used in page replacement algorithms.
The Intel486 DX microprocessor supports dynamic paged virtual memory. Since two level paging is implemented, address translation at two levels would considerably degrade the performance. To overcome this problem, the processor uses a cache memory which keeps track of most recently used pages. This cache is called Translation Lookaside Buffer. Each of the 32 entries of the Translation Lookaside buffer points a (page, page frame) pair.
Segmentation in Intel486
In addition to paging, Intel486 DX supports the segmentation method of memory management. The address translation mechanism is as follows: the 48 bit logical address consists of two parts:
Bits 31 - 00 linear address which is used to find the physical address