George Mason University
Computer Science Department

Course Number: CS465

Course Title: Computer System Architecture

Instructor: Arun Sood

Office: Engineering 5327

Office Phone: 703-993-1524

Office Hours: Tuesday 2:00 to 2:50 PM.

TA: Laxmi Narayan Venkatesh

TA Office Hours:

E-mail: asood (at) gmu (dot) edu.

E-messages must include CS465 as the first 5 characters of the Subject line.  Generally e-mail is good for clarifying or confirming information.   I prefer short and precise messages, and you can expect similar responses. If you find that the reply is too terse, and requires clarification - do not hesitate to see the instructor. If you require more details, a face to face meeting is strongly recommended. E-mail is not a substitute for face to face meetings.

Course Text: Computer Organization and Design: The Hardware / Software Interface by Patterson and Hennessy, Fourth Edition.

Pre-requisites: C or better in CS367. Students not satisfying the prerequisites will be dropped from the class.

Course Content:

This course will follow the text, although supplementary material will be required to cover some of the topics. Some of the earlier chapters and appendices contain review material. We will cover selected parts of other chapters. The focus is on issues and methods involved in designing a computer architecture. The impact of technological and market issues, and the interaction with compiler and operating system design will be explored. Topics include:

Computer system specification
Performance issues
Instruction set selection
ALU design
Architecture design
Datapath selection
Control systems
Single and multiple clocks
Pipelines
Memory hierarchy
I/O architectures.

Course Outcomes:

• Be able to explain the organization of the classical von Neumann machine and its major functional components
• Be able to compare performance of simple system configurations and understand the performance implications of architectural choices
• Be able to demonstrate understanding of instruction set content including types of instructions, addressing modes, and instruction formats.
• Be able to explain how programs written in high level language can be translated into language of hardware and how the hardware executes the resulting program
• Be able to explain how an instruction is executed and the concept of datapaths and control
• Be able to explain basic instruction level parallelism using pipelining and the major hazards that may occur
• Be able to explain the effect of memory latency on running time; be able to describe the use of memory hierarchy to reduce the effective memory latency, in particular, the role of cache and virtual memory; be able to understand the principles of memory management
• Be able to explain the basic I/O implementation and data transfers

Lecture Strategy

Some of the material in the text Chapters has already been covered in the pre-requisite courses. Consequently this material will not be repeated in the class.

Your active participation in the class discussions is encouraged. The instructor is interested in encouraging participation of ALL the students, and any suggestions that will facilitate this effort are solicited.

At the beginning of each class a few minutes will be used to review market and technology trends that have a computer architecture implication. To show the connection between the lectures and existing architectures, students will be required to explore the internet and obtain information about commercial systems.

Homework

All homework must be prepared using a word processor.

Late Policy

Late homework will be accepted with a penalty of 20% per day within 3 days after deadlines and will not be accepted three days after due date, unless under prearranged conditions.

Grade

The grade will be computed on the following basis:

Exam I: 5%; Exam II: 20%; Exam III: 20%; Final: 25%; Quizzes and Homework: 25%, and Class Participation : 5%.

Class Participation is recorded on a daily basis.

Tentative grade cut-offs: A >90%, B > 80%, C >65%, D >50%.

Exam Content

The exams in general will include questions relating to concepts, definitions, analysis and design. You are strongly urged to solve the problems at the end of each chapter. You should not be surprised to find some questions similar to these problems in the various exams.

Exams Schedule (Tentative):

Exam I: January 26; Exam II: March 4; Exam III: April 15; Final: Tues. 11 May 1:30 pm – 4:15 pm.

Last class: April 29.

Spring break: March 7 to March 14

School Calendar

Make - up exams are strongly discouraged.

Award of IN grade:

The IN grade policy as indicated in the catalog will be strictly adhered to. You must provide the necessary back-up documentation (e.g. medical certificate) for your application to be considered favorably. In all circumstances the written request, with all the back up documentation, must be received before the final exam week.

Honor Code

Honor Code procedures will be strictly adhered. Students are required to be familiar with the honor code. You must not utilize unauthorized material or consultation in responding to your tests. Violations of the honor code will be reported. Unless otherwise stated, homework assignments must be based on the student’s own effort.

Please be sure that you are aware of all provisions of the GMU Honor Code
http://www.gmu.edu/catalog/apolicies/honor.html and Computer Science Department Honor Code
http://cs.gmu.edu/wiki/pmwiki.php/HonorCode/CSHonorCodePolicies

Disability

MEMO Email Information

Here are some relevant links 

How to Activate Your Memo Mail Account Using the Web Client

How to Set Up Automatic Forwarding on Your Memo Mail Account

Using the GMU MEMO E-mail from the WWW (new system)