•   When: Friday, February 01, 2019 from 11:00 AM to 12:00 PM
  •   Speakers: Dr. Kirk W. Cameron
  •   Location: ENGR 3507
  •   Export to iCal


From instruction pipelining to multi-issue and prefetching on hyper-threaded, multi-core processors, parallelism (or overlapped work) increases the performance of modern applications and systems. For more than two decades, the field has relied upon a quantitative approach to computer system design that leverages experimental measurements coupled with performance evaluation and prediction. However, despite the evolution, emergence, intricacy, and pervasiveness of designs that increase parallel overlap, application and system performance evaluation techniques have changed little since the 1990's.

A hypothesis of this work is that the elevation of power consumption to a first-class design constraint renders traditional quantitative approaches to system design obsolete. The key observation is that power management alters memory and processor throughput dynamically and that when combined with thread-level parallelism, significant performance overlap effects go undetected using best available parallel performance models. In this talk, I will show how emergent power management techniques require new insights to computation and memory overlap. To this end, I will discuss the Compute-Overlap-Stall (COS) model of parallel computation that enables accurate prediction of the simultaneous performance impact of processor, memory, and thread throttling. The implication of this work is that as power management techniques pervade, new quantitative approaches that isolate the effects of overlap are essential to evaluating future computer system designs.

Speaker Bio

Kirk W. Cameron is Professor of Computer Science at Virginia Tech where he is Director of the stack@cs Center for Computer Systems. Currently, he is Associate Department Head for Research and Engagement
where he stewards department corporate activities with Block.One, Amazon, and the computer science research consortium (CSRC) of 90+ companies.  He served as Associate Department Head for the Graduate Program from 2014-2017, a Visiting Fellow of the U.K. Royal Academy of Engineering at The Queen's University - Belfast from 2017-2018, and was recently elevated to Distinguished Member of the ACM for "outstanding contributions to computing." He is a Green HPC pioneer (Green500, SPECPower, PowerPack, grano.la) and his software has been downloaded by more than 500,000 people in 160+ countries. In addition to NSF and DOE Career Awards, IBM and AMD Faculty Awards, over 100 publications and the HPDC 2017 Best Paper Award, he conceived and created SeeMore, an internationally acclaimed, award-winning, 256-node kinetic sculpture of Raspberry Pi’s. His work consistently appears in The New York Times, The Guardian, Time, Newsweek, etc. and SeeMore was recently named the second best RPi project of all time by MagPi Magazine.

Posted 2 years, 8 months ago